1. Field of the Invention
This invention relates to a highly integrated and large-capacity semiconductor memory device which includes MOS (metal-oxide-semiconductor) transistors.
2. Description of the Prior Art
FIG. 9 shows a memory cell portion of a conventional semiconductor memory device including MOS transistors. The memory device has a semiconductor substrate 70 on which a rectangular active region 72 is formed by an LOCOS isolation method (local oxidation method) or by a trench isolation method. Gate electrodes 73 and 74 are formed from polysilicon in such a manner as to intersect the active region 72. Portions of the active region 72 positioned under the gate electrodes 73 and 74 function as channel regions 82 and 81, respectively. A drain region 76 is formed in a portion of the active region 72 interposed between the gate electrodes 73 and 74. In the other portions of the active region 72 are formed source regions 75 and 77, which are positioned adjacent to the gate electrodes 73 and 74, respectively.
The gate electrode 73, channel region 82, source region 75 and drain region 76 constitute an MOS transistor, while the gate electrode 74, channel region 81, source region 77 and drain region 76 constitute another MOS transistor. The two MOS transistors have the drain region 76 in common.
The drain region 76 is connected to a bit line (not shown) through a bit contact 79. The source regions 75 and 77 are connected to one of the electrodes of a charge storage capacitor (not shown) through storage contacts 78 and 80, respectively.
The above-described two MOS transistors, bit contact 79, storage contacts 78 and 80, and charge storage capacitor constitute a memory cell of the semiconductor memory device. The gate electrodes 73 and 74 function as word lines through which address signals are fed into the memory cell.
In cases where a memory cell such as described above has n-type MOS transistors, the application of a high potential bias to the gate electrode 73 or 74 allows one of the two MOS transistors to be in the on state. At this time, if the memory cell is in the read state, a signal charge stored in the capacitor is transmitted into the drain region 76 through the storage contact 78 or 80, source region 75 or 77 and channel region 82 or 81 of the MOS transistor in the on state. The signal charge is then sent to a sense amplifier (not shown) through the bit contact 79 and the bit line. Conversely, if the memory cell is in the write state, a signal charge is transmitted from the drain region 76 in the reverse direction through the above-mentioned components into the capacitor, where the signal charge is stored.
In the production of MOS transistors of such a memory cell, impurity ions are implanted into an active region to form source and drain regions while providing ohmic contacts between the resulting regions and the electrode material. The impurity ions are usually implanted into, for example, the entire area (impurity-implanted region 71 as shown in FIG. 9) of the MOS transistors. The gate electrodes 73 and 74 function as a mask for the ion implantation, so that the impurity ions can be implanted into the areas corresponding to the source and drain regions to be formed. In this case, a portion of the active region on the drain side becomes the drain region 76, and portions of the active region on the source sides become the source regions 75 and 77.
Most of conventional DRAMs (dynamic random access memories) which are known as semiconductor memory devices have folded bit lines in order to attain high resistance to noise. Thus, when the active regions are rectangular as shown in FIG. 9, the respective memory cells are arranged as shown in FIG. 10. As shown in the figure, active regions 89, 90, 92 and 93 are disposed close to the active region 91. The active regions are arranged in columns parallel to gate electrodes 96 functioning as word lines. The active regions in one column are shifted from those in the columns adjacent thereto by half the pitch of the active regions in each row. For example, as shown in the figure, the active regions 88 and 91 are respectively shifted from the active regions 89 and 92, and also from the active regions 90 and 93, by half the pitch, i.e., by half of the distance between the active regions 88 and 91.
For the formation of an isolation region which electrically isolates one active region from another, a silicon substrate is locally oxidized using the LOCOS isolation method in the production of 4-megabit DRAMs (4M DRAMs) or other memory devices with a relatively low integration level. On the other hand, in the production of 16M DRAMs and 64M DRAMs which are highly integrated memory devices with minute structures, it is necessary to form a narrow isolation region with a width of 0.6 to 0.7 .mu.m and with a width of 0.4 to 0.5 .mu.m, respectively. However, an isolation region with a width of 0.4 to 0.7 .mu.m cannot be formed by the use of the LOCOS isolation method. Thus, for the production of highly integrated memory devices which require a narrow isolation region, the trench isolation method should be used to form the isolation region.
A conventional semiconductor memory device such as described above has the following problems:
1) As shown in FIG. 9, the impurity-implanted region 71 overlaps with the entire surface of the MOS transistors. Thus, during the subsequent heat treatment in the formation of the minute structure of memory cells, the impurity ions previously implanted into the impurity-implanted region 71 will be diffused by heat from the source regions 77 and 75 and the drain region 76 into the channel regions 81 and 82, through the entire boundaries between the channel region 81 and the source region 77 and drain region 76 and also through the entire boundaries between the channel region 82 and the source region 75 and drain region 76. This causes a noticeable short channel effect such as a reduced threshold voltage and a reduced punch through breakdown voltage, thereby increasing leakage current, particularly in an MOS transistor which is the smallest transistor unit used for the memory cell of DRAMs. As a result, it becomes difficult for the capacitor to store signal charges in the storage operation of the memory cells.
2) Since the impurity-implanted region 71 overlaps with the entire surface of the MOS transistors as described above, the total area of the source regions 75 and 77 and drain region 76 becomes relatively large. Thus, the junction capacitance which arises between the silicon substrate 70 and the source and drain regions 77, 75 and 76 increases. In particular, the parasitic capacitance of the bit lines increases, thereby increasing the power consumption and reducing the operation speed.
3) As shown in FIG. 10, in memory devices having folded bit lines, the distances between the active region 91 and the active regions 89, 90, 92 and 93 are half or less of that between the active region 91 and the active region 88. Accordingly, the isolation region to be formed is uneven in width between the respective active regions. It is, however, extremely difficult to form an isolation region with an uneven width by the trench isolation method. Thus, the production of highly-integrated 16M DRAMs or 64M DRAMs requires two isolation methods; i.e., the LOCOS isolation method which enables the formation of an isolation region with an uneven width, and the trench isolation method which enables the formation of a narrow isolation region with a width of 0.4 to 0.7 .mu.m. The use of the two methods causes a complicated production process.